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2004 Microchip Technology Inc.
DS30491C-page 115
PIC18F6585/8585/6680/8680
REGISTER 9-5:
PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2
U-0
R/W-0
U-0
R/W-0
—CMIF
—
EEIF
BCLIF
LVDIF
TMR3IF
CCP2IF
bit 7
bit 0
bit 7
Unimplemented: Read as ‘0’
bit 6
CMIF: Comparator Interrupt Flag bit
1
= The comparator input has changed (must be cleared in software)
0
= The comparator input has not changed
bit 5
Unimplemented: Read as ‘0’
bit 4
EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit
1
= The write operation is complete (must be cleared in software)
0
= The write operation is not complete, or has not been started
bit 3
BCLIF: Bus Collision Interrupt Flag bit
1
= A bus collision occurred while the SSP module (configured in I2C Master mode)
was transmitting (must be cleared in software)
0
= No bus collision occurred
bit 2
LVDIF: Low-Voltage Detect Interrupt Flag bit
1
= A low-voltage condition occurred (must be cleared in software)
0
= The device voltage is above the Low-Voltage Detect trip point
bit 1
TMR3IF: TMR3 Overflow Interrupt Flag bit
1
= TMR3 register overflowed (must be cleared in software)
0
= TMR3 register did not overflow
bit 0
CCP2IF: CCP2 Interrupt Flag bit
Capture mode:
1
= A TMR1 or TMR3 register capture occurred (must be cleared in software)
0
= No TMR1 or TMR3 register capture occurred
Compare mode:
1
= A TMR1 or TMR3 register compare match occurred (must be cleared in software)
0
= No TMR1 or TMR3 register compare match occurred
PWM mode:
Unused in this mode.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
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